Shift registers are used in many applications in digital circuit designs. A typical prior art shift register 10 is illustrated in FIGS. 1A and 1B. FIG. 1A illustrates a four bit serial shift register including four D-type flip-flops 12, 14, 16, and 18 each with complementary latches 20 and 22, as shown in FIG. 1B. Each flip-flop of the shift register 10 includes a data input terminal D, a pair of clock signal input lines CA and CB, and a data output terminal Q. The outputs Q of the flip-flops 12, 14, and 16 form the data inputs D for the next or subsequent flip-flop 14, 16, and 18 in the series.
As seen in FIG. 1B, the transfer of data from the data input terminal D into the first latch 20 is controlled by a transistor pass gate 30, and the transfer of data from the first latch 20 into the second latch 22 is controlled by a second transistor pass gate 32. A pair of clock signals CLK and CLKB for the shift register 10 is physically connected to the respective pass gates 30 and 32 of each flip-flop via the clock signal input lines CA and CB. Each flip-flop is a positive edge triggered flip-flop, which means that data is shifted from input D to output Q on the rise of the clock signal CLK and on the fall of the clock signal CLKB.
FIG. 2 illustrates a partial timing diagram for clock signals CLK and CLKB as applied simultaneously to each flip-flop 12, 14, 16, and 18. As CLK reaches a positive (rise) edge and CLKB reaches a negative (fall) edge the following data transfer occurs. Data DIN is shifted from data input terminal 21 and latched to output QA of flip-flop 12 (FIG. 1). Data A, previously stored in flip-flop 12, is shifted and latched to output QB of flip-flop 14. Data B, previously stored in flip-flop 14, is shifted and latched to output QC of flip-flop 16. Data C, previously stored in flip-flop 16 is transferred and latched to output QD of latch 18. Data D, previously stored in latch 18, is shifted out on to data output terminal 23. On the next positive edge of CLK and negative edge of CLKB, data is shifted through to the next subsequent flip-flop. DIN, A, B, C and D represent bit data. DIN, A, B, C and D represent values that may all be the same, different or that may be various combinations of values.
A problem with prior shift devices, like the one just described, is that they take up much silicon space. If the area for one latch (typically 5 transistors) is represented by Y, then the amount of silicon required for a four-bit shift register having two latches per bit stored is Y(area)×2(latches)×4(bits)=8Y. An additional problem with some prior art registers is that much power is consumed where the clock signal input line operates to provide an input clock signal to all of the flip-flops simultaneously.
Therefore, it is an object of the present invention to provide a shift register device that efficiently utilizes silicon space.
It is a further object of the present invention to provide a shift register device that efficiently consumes power during operation.